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LH531024
FEATURES * 65,536 words x 16 bit organization * Access time: 100 ns (MAX.) * Power consumption: Operating: 412.5 mW (MAX.) Standby: 550 W (MAX.) * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * JEDEC standard EPROM pinout (DIP) * Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) DESCRIPTION
The LH531024 is a mask-programmable ROM organized as 65,536 x 16 bits. It is fabricated using silicon-gate CMOS process technology.
NC CE D15 D14 D13 D12 D11 D10 D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 OE 40-PIN DIP 40-PIN SOP
CMOS 1M (64K x 16) MROM
PIN CONNECTIONS
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC NC NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
531024-1
Figure 1. Pin Connections for DIP and SOP Packages
44-PIN PLCC TOP VIEW
D12 D11 D10 D9 D8 GND NC D7 D6 D5 D4
7 8 9 10 11 12 13 14 15 16
D13 D14 D15 CE NC NC VCC NC NC A15 A14
6 5 4 3 2 1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30
A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5
29 17 18 19 20 21 22 23 24 25 26 27 28
D3 D2 D1 D0 OE NC A0 A1 A2 A3 A4
531024-2
Figure 2. Pin Connections for QFJ (PLCC) Package
1
LH531024
CMOS 1M MROM
A15 37 A14 36 A13 35 A12 34 A11 33 A10 32 A9 31 A8 29 A7 28 A6 27 A5 26 A4 25 A3 24 A2 23 A1 22 A0 21
MEMORY MATRIX (65,536 x 16) ADDRESS DECODER ADDRESS BUFFER
COLUMN SELECTOR
CE 2
CE BUFFER
TIMING GENERATOR
SENSE AMPLIFIER
OE 20
OE BUFFER
OUTPUT BUFFER
40 VCC
11 30 GND
19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14D15
531024-3
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH531024 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A15 D0 - D15 CE
Address input Data output Chip Enable input
OE VCC GND
Output enable input Power supply (+5 V) Ground
2
CMOS 1M MROM
LH531024
A15 41 A14 40 A13 39 A12 38 A11 37 A10 36 A9 35 A8 32 A7 31 A6 30 A5 29 A4 28 A3 27 A2 26 A1 25 A0 24
MEMORY MATRIX (65,536 x 16) ADDRESS DECODER ADDRESS BUFFER
COLUMN SELECTOR
CE 3
CE BUFFER
TIMING GENERATOR
SENSE AMPLIFIER
OE 22
OE BUFFER
OUTPUT BUFFER
44 VCC NOTE: Pin numbers apply to the 44-pin QFJ.
12 34 GND
21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14D15
531024-4
Figure 4. LH531024 Block Diagram
3
LH531024
CMOS 1M MROM
TRUTH TABLE
CE OE D0 - D15 SUPPLY CURRENT NOTE
H L L
NOTE: 1. X = H or L.
X H L
High-Z D0 - D15
Standby (ISB) Operating (ICC)
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage Input voltage Output voltage Operating temperature Storage temperature
VCC VIN VOUT Topr Tstg
-0.3 to +7.0 -0.3 to V CC +0.3 -0.3 to V CC +0.3 0 to +70 - 65 to +150
V V V C C
RECOMMENDED OPERATING CONDITIONS (TA = 0C to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input `Low' voltage Input `High' voltage Output `Low' voltage Output `High' voltage Input leakage current Output leakage current
VIL V IH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 ISB2 CIN COUT I OL = 2.0 mA I OH = -400 A V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 100 ns t RC = 1 s t RC = 100 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz T A = 25C
-0.3 2.2 2.4
0.8 VCC + 0.3 0.4 10 10 75 65 70 60 3 100 10 10
V V V V A A mA mA mA mA mA A pF pF 3 1 2
Operating current
Standby current Input capacitance Output capacitance
NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
4
CMOS 1M MROM
LH531024
AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z
tRC tAA tACE tOE tOH tCHZ tOHZ
100 100 100 50 5 50 50
ns ns ns ns ns ns ns 1
NOTE: 1. This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude Input signal rise time Input/output reference level Output load condition
0.4 V to 2.6 V 10 ns 1.5 V 1TTL +100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the V CC pin and the GND pin.
tRC
A0 - A15 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOH tOHZ tCHZ
D0 - D15
DATA VALID
NOTE: Data becomes valid after the intervals, tAA, tACE, and tOE, from address input, chip enable, and output enable, respectively have been met.
531024-5
Figure 5. Timing Diagram
5
LH531024
CMOS 1M MROM
PACKAGE DIAGRAMS
40DIP (DIP040-P-0600)
40 21
DETAIL
13.45 [0.530] 12.95 [0.510]
1 52.30 [2.059] 51.70 [2.035]
20
0 TO 15 0.30 [0.012] 0.20 [0.008]
4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
40DIP
40-pin, 600-mil DIP
40SOP (SOP040-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 21
0.50 [0.020] 0.30 [0.012]
40
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 26.50 [1.043] 26.10 [1.028]
20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
40SOP
40-pin, 525-mil SOP
6
CMOS 1M MROM
LH531024
44QFJ (QFJ044-P-S650)
1.27 [0.050] TYP. C1.1 6 1 44 40
7
39
16.60 [0.654] 17.60 [0.693] 17.40 [0.685]
16.00 [0.630] 15.20 [0.598]
17
29
0.56 [0.022] 0.36 [0.014]
18 16.60 [0.654] 17.60 [0.693] 17.40 [0.685]
28 0.85 [0.033] 2.80 [0.110] 2.40 [0.094] 1.80 [0.071] 0.25 [0.010] 4.60 [0.181] 4.20 [0.165] 2.35 [0.093]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
44QFJ-1
44-pin, 650-mil QFJ (PLCC)
ORDERING INFORMATION
LH531024 Device Type X Package
D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) U 44-pin, 650-mil QFJ (PLCC) (QFJ044-P-S650) CMOS 1M (64K x 16) Mask-Programmable ROM Example: LH531024N (CMOS 1M (64K x 16) Mask-Programmable ROM, 40-pin, 525-mil SOP)
531024-6
7

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